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publication number S29AL008J_00 revision 11 issue date april 12, 2012 S29AL008J S29AL008J cover sheet 8 megabit (1 m x 8-bit/512 k x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet notice to readers: this document states the cu rrent technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have be en in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinatio ns offered may occur.
2 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. dee ms the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. however, typographical or specificati on corrections, or modifications to the valid com- binations offered may occur. publication number S29AL008J_00 revision 11 issue date april 12, 2012 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ? manufactured on 110 nm process technology ? fully compatible with 200 nm s29al008d ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? one 16 kbyte, two 8 kbyte, one 32 kbyte, and fifteen 64 kbyte sectors (byte mode) ? one 8 kword, two 4 kword, one 16 kword, and fifteen 32 kword sectors (word mode) ? sector group protection features ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? top or bottom boot block configurations available ? compatibility with jedec standards ? pinout and software compatible with single-power supply flash ? superior inadvertent write protection performance characteristics ? high performance ? access times as fast as 55 ns ? extended temperature range (?40c to +125c) ? ultra low power consumption (typical values at 5 mhz) ? 0.2 a automatic sleep mode current ? 0.2 a standby mode current ? 7 ma read current ? 20 ma program/erase current ? cycling endurance: 1,000,000 cycles per sector typical ? data retention: 20 years typical package options ? 48-ball fine-pitch bga ? 48-pin tsop software features ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp# input pin ? for boot sector devices: at v il , protects first or last 16 kbyte sector depending on boot configuration (top boot or bottom boot) S29AL008J 8 megabit (1 m x 8-bit/512 k x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet
4 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet general description the S29AL008J is a 8 mbit, 3.0 volt-only flash memory organized as 1,048,576 bytes or 524,288 words. the device is offered in 48-ball fine-pitch bga (0.8 mm pitch), and 48-pin tsop packages. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. this device is designed to be programmed in-system with the standard system 3.0 volt v cc supply. a 12.0 v v pp or 5.0 v cc are not required for write or erase operations. the device can also be programmed in standard eprom programmers. the device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provi ded for the program and erase operations. the S29AL008J is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register usin g standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data n eeded for the programming and erase operations. reading data out of the device is similar to re ading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that automati cally times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program dat a instead of four. device erasure occurs by executing the er ase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically prepr ograms the array (if it is not already programmed) before executing the erase op eration. during erase, the device au tomatically times the erase pulse widths and verifies proper cell margin. the host system can detect wh ether a program or erase operation is co mplete by observing the ry/by# pin, or by reading the dq7 (dat a# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of t he sectors of memory. this can be ac hieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to , any sector that is not selected fo r erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitr y. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. spansion flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
april 12, 2012 S29AL008J_00_11 S29AL008J 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 special handling instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 S29AL008J standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 7. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 program and erase operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 7.8 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 sector group protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.11 temporary sector group unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8. secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 factory locked: secured silicon sector programmed and protected at the factory . . . . . . 22 8.2 customer lockable: secured s ilicon sector not programmed or protected at the factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 9. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.4 enter secured silicon sector/exit secured silicon sector command sequence . . . . . . . . . 28 10.5 word/byte program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.6 unlock bypass command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.7 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.8 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.9 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.10 command definitions table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 15. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 17.3 word/byte configuration (byte#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 17.4 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 17.5 temporary sector group unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.6 alternate ce# controlled erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 19. tsop and bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 20. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.1 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.2 vbk048?48-ball fine-pitch ball grid array (bga) 8.15 mm x 6.15 mm . . . . . . . . . . . . . . . 51 21. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
april 12, 2012 S29AL008J_00_11 S29AL008J 7 data sheet figures figure 3.1 48-pin standard tsop (ts048). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.2 48-ball fine-pitch bga (vbk048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7.1 temporary sector group unprotect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7.2 in-system sector group protect/unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8.1 secured silicon sector protect verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11.2 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 13.2 maximum positive overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 15.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16.1 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17.1 read operations timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17.2 reset# timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17.3 byte# timings for read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17.4 byte# timings for write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17.5 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17.6 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17.7 back to back read/write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17.8 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.9 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.10 dq2 vs. dq6 for erase and erase suspend operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.11 temporary sector group unprotect/timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.12 sector group protect/unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.13 alternate ce# controlled write operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet tables table 7.1 S29AL008J device bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7.2 S29AL008J top boot block sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7.3 secured silicon sector addresses (top boot). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7.4 S29AL008J bottom boot block sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.5 secured silicon sector addresses (bottom boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.6 S29AL008J autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7.7 S29AL008J top boot device sect or/sector group protection . . . . . . . . . . . . . . . . . . . . . . . 19 table 7.8 S29AL008J bottom boot device sector/sector group protection. . . . . . . . . . . . . . . . . . . . . 19 table 9.1 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 10.1 S29AL008J command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11.1 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
april 12, 2012 S29AL008J_00_11 S29AL008J 9 data sheet 1. product selector guide note see ac characteristics on page 41 for full specifications. 2. block diagram family part number S29AL008J speed option voltage range: v cc = 2.7-3.6v 70 v cc = 3.0-3.6v 55 max access time, ns (t acc )5570 max ce# access time, ns (t ce )5570 max ce# access time, ns (t oe )3030 input/output buffers x-decoder y- d e c o d e r chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# wp# ce# oe# dq0?dq15 (a-1) sector switches ry/by# reset# data latch y- g a t i n g cell matrix address latch a0?a18
10 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 3. connection diagrams figure 3.1 48-pin standard tsop (ts048) figure 3.2 48-ball fine-pitch bga (vbk048) 3.1 special handling instructions special handling is required for flash memory products in bga packages. flash memory devices in bga packages may be damage d if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150 c for prolonged periods of time. a1 a15 a1 8 a14 a1 3 a12 a11 a10 a9 a 8 nc nc we# re s et# nc wp# ry/by# a17 a7 a6 a5 a4 a 3 a2 1 16 2 3 4 5 6 7 8 17 1 8 19 20 21 22 2 3 24 9 10 11 12 1 3 14 15 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq1 3 dq9 dq1 dq 8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq 3 dq10 4 8 33 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 25 3 2 3 1 3 0 29 2 8 27 26 a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a 3 b 3 c 3 d 3 e 3 f 3 g 3 h 3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a1 3 dq1 3 dq6 dq14 dq7 a11 a10 a 8 a9 v cc dq4 dq12 dq5 nc nc re s et# we# dq11 dq 3 dq10 dq2 nc a1 8 wp# ry/by# dq9 dq1 dq 8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a 3 (top view, balls facing down)
april 12, 2012 S29AL008J_00_11 S29AL008J 11 data sheet 4. pin configuration 5. logic symbol a0?a18 19 addresses dq0?dq14 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) byte# selects 8-bit or 16-bit mode ce# chip enable oe# output enable we# write enable wp# write protect: the wp# contains an internal pull-up; when unconnected, wp is at v ih . reset# hardware reset ry/by# ready/busy output v cc 3.0 volt-only single power supply (see product selector guide on page 9 for speed options and voltage supply tolerances) v ss device ground nc pin not connected internally 19 16 or 8 dq0?dq15 (a-1) a0?a18 ce# oe# we# reset# byte# ry/by# wp#
12 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 6. ordering information 6.1 S29AL008J standard products spansion standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes 1. type 0 is standard. specify other options as required. 2. type 1 is standard. specify other options as required. 3. tsop package markings omit packing type designator from ordering part number. 4. bga package marking omits leading s29 and packing type designator from ordering part number. S29AL008J 70 t f i 01 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number 01 = v cc = 2.7-3.6v, top boot sector device (cfi support) 02 = v cc = 2.7-3.6v, bottom boot sector device (cfi support) 03 = v cc = 2.7-3.6v, top boot sector device (no cfi support) 04 = v cc = 2.7-3.6v, bottom boot sector device (no cfi support) r1 = v cc = 3.0-3.6v, top boot sector device (cfi support) r2 = v cc = 3.0-3.6v, bottom boot sector device (cfi support) temperature range i = industrial (-40c to +85c) n = extended (-40c to +125c) package material set f = pb-free h = low-halogen, pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package speed option 55 = 55 ns access speed 70 = 70 ns access speed device number/description S29AL008J 8 megabit flash memory manufactured using 110 nm process technology 3.0 volt-only read, program, and erase S29AL008J valid combination package description device number speed option package type, material, and temperature range model number packingtype S29AL008J 55 tfi, tfn r1, r2 0, 3 (note 1) ts048 (note 3) tsop bfi, bfn, bhi, bhn 0, 2, 3 (note 1) vbk048 (note 4) fine-pitch bga 70 tfi, tfn 01, 02 0, 3 (note 1) ts048 (note 3) tsop bfi, bfn, bhi, bhn 0, 2, 3 (note 1) vbk048 (note 4) fine-pitch bga tfi 03, 04 0, 3 (note 1) ts048 (note 3) tsop bfn, bhn 0, 2, 3 (note 1) vbk048 (note 4) fine-pitch bga
april 12, 2012 S29AL008J_00_11 S29AL008J 13 data sheet 7. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is composed of latc hes that store the commands, along with the address and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine output s dictate the function of the device. table 7.1 lists the device bus operations, the inputs and control levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. legend l = logic low = v il; h = logic high = v ih; v id = 8.5 v to 12.5 v; x = don?t care; a in = address in; d out = data out notes 1. address in = amax:a0 in word mode (byte#=v ih ), address in = amax:a-1 in byte mode (byte#=v il ). sector addresses are amax to a12 in both word mode and byte mode. 2. the sector group protect and sector group unprotect f unctions may also be implemented via programming equipment. see sector group protection/unprotection on page 18. 3. if wp# = v il , the outermost sector remains protected (determined by device configuration). if wp# = v ih , the outermost sector protection depends on whether the sector was last protected or unprotected using the method described in section 7.10, sector group protection/ unprotection on page 18 . the wp# contains an internal pull- up; when unconnected, wp is at v ih . 4. d in or d out as required by command sequence, data polli ng, or sector group protection algorithm. 7.1 word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configuration. if the byte# pin is set at logic 1 , the device is in word configur ation, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. 7.2 requirements for reading array data to read array data from the outputs, the syst em must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output cont rol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the de vice outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses table 7.1 S29AL008J device bus operations operation ce# oe# we# reset# wp# addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l h (note 3) a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v x x high-z high-z high-z output disable l h h h x x high-z high-z high-z reset x x x l x x high-z high-z high-z sector group protect (2) (3) lhl v id h sector address, a6 = l, a3 = a2 = l, a1 = h, a0 = l (note 4) xx sector group unprotect (2) (3) lhl v id h sector address, a6 = h, a3 = a2 = l, a1 = h, a0 = l (note 4) xx temporary sector group unprotect xxx v id ha in (note 4) (note 4) high-z
14 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet on the device address inputs produce valid data on the device data outputs. the de vice remains enabled for read access until the command register contents are altered. see reading array data on page 27 for more information. refer to the ac read operations on page 41 for timing specifications and to figure 17.1 on page 41 for the timing diagram. i cc1 in dc characteristics on page 39 represents the active current specification for reading array data. 7.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whet her the device accepts program data in bytes or words. see word/byte configuration on page 13 for more information. the device features an unlock bypass mode to facilitate faster programm ing. once the device enters the unlock bypass mode, only two writ e cycles are required to program a word or byte, instead of four. word/ byte program command sequence on page 28 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table 7.2 on page 16 and table 7.4 on page 17 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the command definitions on page 27 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autose lect command sequence, the device en ters the autoselect mode. the system can then read autoselec t codes from the internal register (whi ch is separate from the memory array) on dq7?dq0. standard read cycle timing s apply in this mode. refer to autoselect mode on page 18 and autoselect command sequence on page 27 for more information. i cc2 in dc characteristics on page 39 represents the active current specification for the write mode. ac characteristics on page 41 contains timing specification tables and timing diagrams for write operations. 7.4 program and erase operation status during an erase or program operatio n, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to write operation status on page 33 for more information, and to ac characteristics on page 41 for timing diagrams. 7.5 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 and i cc4 represents the standby current spec ification shown in the table in dc characteristics on page 39 .
april 12, 2012 S29AL008J_00_11 S29AL008J 15 data sheet 7.6 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics on page 39 represents the automatic sleep mode current specification. 7.7 reset#: hardware reset pin the reset# pin provides a hardware me thod of resetting the de vice to reading arra y data. when the system drives the reset# pin to v il for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state ma chine to reading array data. the operation that was interrupted should be reinitiated once the device is re ady to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3/0.1 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmwar e from the flash memory. note that the ce# pin should only go to v il after reset# has gone to v ih . keeping ce# at v il from power up through the first read could cause the first read to retrieve erroneous data. if reset# is asserted during a program or er ase operation, the ry /by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase operat ion is not executing (ry/by# pin is 1 ), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the tables in ac characteristics on page 41 for reset# parameters and to figure 17.2 on page 42 for the timing diagram.
16 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 7.8 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins are placed in the high impedance state. note address range is a18:a-1 in byte mode and a19:a0 in word mode. see word/byte configuration on page 13 . table 7.2 S29AL008J top boot block sector addresses sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) (x8) address range (x16) address range sa0 0 0 0 0 x x x 64/32 00000h?0ffffh 00000h?07fffh sa1 0 0 0 1 x x x 64/32 10000h?1ffffh 08000h?0ffffh sa2 0 0 1 0 x x x 64/32 20000h?2ffffh 10000h?17fffh sa3 0 0 1 1 x x x 64/32 30000h?3ffffh 18000h?1ffffh sa4 0 1 0 0 x x x 64/32 40000h?4ffffh 20000h?27fffh sa5 0 1 0 1 x x x 64/32 50000h?5ffffh 28000h?2ffffh sa6 0 1 1 0 x x x 64/32 60000h?6ffffh 30000h?37fffh sa7 0 1 1 1 x x x 64/32 70000h?7ffffh 38000h?3ffffh sa8 1 0 0 0 x x x 64/32 80000h?8ffffh 40000h?47fffh sa9 1 0 0 1 x x x 64/32 90000h?9ffffh 48000h?4ffffh sa10 1 0 1 0 x x x 64/32 a0000h?affffh 50000h?57fffh sa11 1 0 1 1 x x x 64/32 b0000h?bffffh 58000h?5ffffh sa12 1 1 0 0 x x x 64/32 c0000h?cffffh 60000h?67fffh sa13 1 1 0 1 x x x 64/32 d0000h?dffffh 68000h?6ffffh sa14 1 1 1 0 x x x 64/32 e0000h?effffh 70000h?77fffh sa15 1 1 1 1 0 x x 32/16 f0000h?f7fffh 78000h?7bfffh sa161111100 8/4 f80 00h?f9fffh 7c000h?7cfffh sa171111101 8/4 fa00 0h?fbfffh 7d000h?7dfffh sa18111111x 16/8 fc000h? fffffh 7e000h?7ffffh table 7.3 secured silicon sector addresses (top boot) sector size (bytes/words) x8 address range x16 address range 256/128 fff00h?fffffh 7ff80h?7ffffh
april 12, 2012 S29AL008J_00_11 S29AL008J 17 data sheet note address range is a18:a-1 in byte mode and a19:a0 in word mode. see the word/byte configuration on page 13 . table 7.4 S29AL008J bottom boot block sector addresses sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) (x8) address range (x16) address range sa0000000x 16/8 000 00h?03fffh 00000h?01fffh sa10000010 8/4 040 00h?05fffh 02000h?02fffh sa20000011 8/4 060 00h?07fffh 03000h?03fffh sa3 0 0 0 0 1 x x 32/16 08000h?0ffffh 04000h?07fffh sa4 0 0 0 1 x x x 64/32 10000h?1ffffh 08000h?0ffffh sa5 0 0 1 0 x x x 64/32 20000h?2ffffh 10000h?17fffh sa6 0 0 1 1 x x x 64/32 30000h?3ffffh 18000h?1ffffh sa7 0 1 0 0 x x x 64/32 40000h?4ffffh 20000h?27fffh sa8 0 1 0 1 x x x 64/32 50000h?5ffffh 28000h?2ffffh sa9 0 1 1 0 x x x 64/32 60000h?6ffffh 30000h?37fffh sa10 0 1 1 1 x x x 64/32 70000h?7ffffh 38000h?3ffffh sa11 1 0 0 0 x x x 64/32 80000h?8ffffh 40000h?47fffh sa12 1 0 0 1 x x x 64/32 90000h?9ffffh 48000h?4ffffh sa13 1 0 1 0 x x x 64/32 a0000h?affffh 50000h?57fffh sa14 1 0 1 1 x x x 64/32 b0000h?bffffh 58000h?5ffffh sa15 1 1 0 0 x x x 64/32 c0000h?cffffh 60000h?67fffh sa16 1 1 0 1 x x x 64/32 d0000h?dffffh 68000h?6ffffh sa17 1 1 1 0 x x x 64/32 e0000h?effffh 70000h?77fffh sa18 1 1 1 1 x x x 64/32 f0000h?fffffh 78000h?7ffffh table 7.5 secured silicon sector addresses (bottom boot) sector size (bytes/words) x8 address range x16 address range 256/128 000000h?0000ffh 00000h?0007fh
18 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 7.9 autoselect mode the autoselect mode provides manu facturer and device id entification, and sect or group protection verification, through identifier codes output on dq7?dq0 . this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-syst em through the co mmand register. when using programming equipment, the autoselect mode requires v id (8.5 v to 12.5 v) on address pin a9. address pins a6 and a3?a0 must be as shown in table 7.6 . in addition, when verifying sector group protection, the sector address must appear on t he appropriate highest order address bits (see table 7.2 on page 16 and table 7.4 on page 17 ). table 7.6 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 10.1 on page 32 . this method does not require v id . see command definitions on page 27 for details on using the autoselect mode. legend l = logic low = v il; h = logic high = v ih; sa = sector address; x = don?t care note the autoselect codes may also be accessed in-system via command sequences. see table 10.1 on page 32 . 7.10 sector group protection/unprotection the hardware sector group protection feature disables both program and erase operations in any sector group (see table 7.2 on page 16 to table 7.5 on page 17 ). the hardware sector gr oup unprotection feature re-enables both program and erase operations in pr eviously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the reset# pin only, and ca n be implemented either in- system or via programming equipment. figure 7.2 on page 21 shows the algorithms and figure 17.11 on page 47 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unprotect ed sector groups must first be protec ted prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unprote cted. spansion offers the option of programming and protecting sector groups at its fa ctory prior to shipping the device th rough spansion programming service. contact a spansion representative for details. it is possible to determine whether a sector group is protected or unprotected. see autoselect mode on page 18 for details. table 7.6 S29AL008J autoselect codes (high voltage method) description mode ce# oe# we# a18 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : spansion l l h x v id xlxlll x 01h device id: S29AL008J (top boot block) word l l h xv id xlxllh 22h dah byte l l h x dah device id: S29AL008J (bottom boot block) word l l h xv id xlxllh 22h 5bh byte l l h x 5bh sector group protection verification l l h sa v id xlxlhl x 01h (protected) x 00h (unprotected) secured silicon sector indicator bit (dq7) top boot block ll hxv id xlxlhh x 8eh (factory locked) 0eh (not factory locked) secured silicon sector indicator bit (dq7) bottom boot block ll hxv id xlxlhh x 96h (factory locked) 16h (not factory locked)
april 12, 2012 S29AL008J_00_11 S29AL008J 19 data sheet table 7.7 S29AL008J top boot device sector/sector group protection sector / sector block a18 a17 a16 a15 a14 a13 a12 sector / sector block size sa0-sa3 0 0 x x x x x 256 (4x64) kbytes sa4-sa7 0 1 x x x x x 256 (4x64) kbytes sa8-sa11 1 0 x x x x x 256 (4x64) kbytes sa12-sa13 1 1 0 x x x x 128 (2x64) kbytes sa14 1 1 1 0 x x x 64 kbytes sa15 1 1 1 1 0 x x 32 kbytes sa16 1111100 8 kbytes sa17 1111101 8 kbytes sa18 1 1 1 1 1 1 x 16 kbytes table 7.8 S29AL008J bottom boot device sector/sector group protection sector / sector block a18 a17 a16 a15 a14 a13 a12 sector / sector block size sa0 000000x 16 kbytes sa1 0000010 8 kbytes sa2 0000011 8 kbytes sa3 00001xx 32 kbytes sa4 0 0 0 1 x x x 64 kbytes sa5-sa6 0 0 1 x x x x 128 (2x64) kbytes sa7-sa10 0 1 x x x x x 256 (4x64) kbytes sa11-sa14 1 0 x x x x x 256 (4x64) kbytes sa15-sa18 1 1 x x x x x 256 (4x64) kbytes
20 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 7.11 temporary sector group unprotect this feature allows temporary unprotection of previous ly protected sector groups to change data in-system. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sector groups can be pr ogrammed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sector group s are protected again. figure 7.1 shows the algorithm, and figure 17.11 on page 47 shows the timing diagrams, for this feature. figure 7.1 temporary sector group unprotect operation notes 1. all protected sector groups unprotected. (if wp# = v il , the highest or lowest address sector remains protected for uniform sector devices; the top or bottom two address sectors remains protected for boot sector devices). 2. all previously protected sector groups are protected once again. start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1)
april 12, 2012 S29AL008J_00_11 S29AL008J 21 data sheet figure 7.2 in-system sector group pr otect/unprotect algorithms sector group protect: write 60h to sector group address with a6 = 0, a3 = a2 = 0, a1 = 1, a0 = 0 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6 = 0, a3 = a2 = 0, a1 = 1, a0 = 0 read from sector group address with a6 = 0, a3 = a2 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete ye s ye s no plscnt = 25? ye s device failed increment plscnt temporary sector group unprotect mode no sector groupunprotect: write 60h to sector address with a6 = 1, a3 = a2 = 0, a1 = 1, a0 = 0 set up first sector group address wait 1.5 ms verify sector group unprotect: write 40h to sector address with a6 = 1, a3 = a2 = 0, a1 = 1, a0 = 0 read from sector groupaddress with a6 = 1, a3 = a2 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete ye s no plscnt = 1000? ye s device failed increment plscnt temporary sector group unprotect mode no all sectors protected? ye s protect all sectors: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no ye s no ye s no no ye s no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
22 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 8. secured silicon sector flash memory region the secured silicon sector feature provides a 256-by te flash memory region that enables permanent part identification through an electronic serial number (esn ). the secured silicon sector uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the fact ory and cannot be changed, which prevents cloning of a factory-locked part. this ensures the security of the esn once the product is shipped to the field. spansion offers the device with the secured silicon sect or either factory-locked or customer-lockable. the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a 1. the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customer s to utilize the that sector in an y manner they choose. the customer- lockable version has the secured silicon sector indicator bit permanently set to a 0. thus, the secured silicon sector indicator bit prevents customer-lockabl e devices from being used to replace devices that are factory locked. the system accesses the secured silicon sector through a command sequence (see enter secured silicon sector/exit secured silicon sector command sequence on page 28 ). after the system writes the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until t he system issues the exit secured silicon sector command sequence, or until pow er is removed from the device. on power-up, or following a hardware reset, the device revert s to sending commands to the boot sectors. 8.1 factory locked: secured silicon sector programmed and protected at the factory in a factory locked device, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modifi ed in any way. the device is available pre-programmed with one of the following: ? a random, secure esn only. ? customer code through the expressflash service. ? both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device has the 16-byte (8-word) esn in sector 0 at addresses 00000h?0000fh in byte mode (or 00000h?00007h in word mode). in the top boot device, the esn is in sector 18 at addresses ffff 0h?fffffh in byte mode (or 7fff8h?7ffffh in word mode). customers may opt to have their code programmed by spansion through the spansion expressflash service. spansion programs the cust omer?s code, with or without the random esn. the devices are then shipped from the spansion factory with the secured s ilicon sector permanently locked. contact a spansion representative for details on using the spansion expressflash service. 8.2 customer lockable: secured s ilicon sector not programmed or protected at the factory the customer lockable version allows the secured silicon sector to be programmed once, and then permanently locked after it ships from spansion. note that the unlock bypass functions is not available when programming the secured silicon sector. the secured silicon sector area can be protected using the following procedures: ? write the three-cycle enter secured silicon region command sequence, and then follow the in-system sector group protect algorithm as shown in figure 7.2 on page 21 , substituting the sector group address with the secured silicon sector group address (a0=0, a1=1, a2=0, a3=1, a4=1, a5 =0, a6=0, a7=0). note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 8.1 on page 23 . once the secured silicon sector is locked and verified, the system must wr ite the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array.
april 12, 2012 S29AL008J_00_11 S29AL008J 23 data sheet the secured silicon sector protection must be used wit h caution since, once protec ted, there is no procedure available for unprotecting the secured silicon sector area , and none of the bits in the secured silicon sector memory space can be modified in any way. figure 8.1 secured silicon sector protect verify write 60h to a ny a ddre ss write 40h to s ec s i s ector a ddre ss with a0=0, a1=1, a2=0, a 3 =1, a4=1, a5=0, a6=0, a7=0 s ta rt re s et# = v id w a it 1 m s re a d from s ec s i s ector a ddre ss with a0=0, a1=1, a2=0, a 3 =1, a4=1, a5=0, a6=0, a7=0 if d a t a = 00h, s ec s i s ector i s u nprotected. if d a t a = 01h, s ec s i s ector i s protected. remove v id from re s et# write re s et comm a nd s ec s i s ector protect verify complete
24 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 9. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 9.1 to table 9.4 on page 25 . in word mode, the upper address bits (a7?msb) must be all zeros. to te rminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 9.1 to table 9.4 on page 25 . the system must write the reset command to return the device to the autoselect mode. table 9.1 cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 9.2 system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0003h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
april 12, 2012 S29AL008J_00_11 S29AL008J 25 data sheet table 9.3 device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0014h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 000eh 0000h 0000h 0001h erase block region 4 information table 9.4 primary vendor-specific ex tended query (sheet 1 of 2) addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 000ch address sensitive unlock 0 = required, 1 = not required process technology (bits 5-2) 0011b = 0.11 m floating gate nor 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector group protect 0 = not supported, x= number of sectors in smallest sector group 48h 90h 0001h sector group temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector group protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0000h acc (acceleration) supply minimum 00 = not supported, d7-d4: volt, d3-d0: 100mv 4eh 9ch 0000h acc (acceleration) supply maximum 00 = not supported, d7-d4: volt, d3-d0: 100mv
26 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 9.1 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10.1 on page 32 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or pr ogramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down tran sitions, or from system noise. 9.1.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 9.1.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 9.1.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 9.1.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is aut omatically reset to reading array data on power-up. 4fh 9eh 00xxh wp# protection 00 = uniform device without wp protect 01 = boot device with top and bottom wp protect 02 = bottom boot device with wp protect 03 = top boot device with wp protect 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 06 = uniform device with all sectors wp protect 50h a0h 00xxh program suspend 00 = not supported, 01 = supported table 9.4 primary vendor-specific ex tended query (sheet 2 of 2) addresses (word mode) addresses (byte mode) data description
april 12, 2012 S29AL008J_00_11 S29AL008J 27 data sheet 10. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 10.1 on page 32 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens fi rst. refer to the appropriate timing diagrams in ac characteristics on page 41 . 10.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command , the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase- suspended sectors, the device outpu ts status data. after completing a programming operation in the erase suspend mode, the system may once again r ead array data with the same exception. see erase suspend/ erase resume commands on page 30 for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see reset command on page 27 . see also requirements for reading array data on page 13 for more information. the read operations on page 41 provides the read parameters, and figure 17.1 on page 41 shows the timing diagram. 10.2 reset command writing the reset command to the device resets the devic e to reading array data. address bits are don?t care for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the device to reading a rray data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the device to readi ng array data (also applies to programming in erase suspend mode). once programming begins, however, th e device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). 10.3 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 10.1 on page 32 shows the address and data requirements. this method is an alternative to that shown in table 7.6 on page 18 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mo de, and the system may read at any address any number of times, without initia ting another command sequence. a read cycle at address xx00h retrieves the manufactur er code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protect ed, or 00h if it is unprotected. refer to table 7.2 on page 16 and table 7.4 on page 17 for valid sector addresses. the system must write the reset command to exit th e autoselect mode and return to reading array data.
28 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 10.4 enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing a random , sixteen-byte electronic serial number (esn). the system can access the secured silicon sector region by issu ing the three-cycle enter secured silicon sector command sequence. t he device continues to a ccess the secured silicon sector region until the system issues the four-cycle exit secured silicon sector co mmand sequence. the exit secured silicon sector command sequence returns the device to normal operation. table 10.1 on page 32 shows the addresses and data requirements for both command sequences. note that the unlock bypass mode is not available when the device ent ers the secured silicon sector. see also secured silicon sector flash memory region on page 22 for further information. 10.5 word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequen ce is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 10.1 on page 32 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7, dq6, or ry/by#. see write operation status on page 33 for information on these status bits. any commands written to the device during the embe dded program algorithm are ignored. note that a hardware reset immediately terminates the programming oper ation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1 , or cause the data# polling algorithm to indicate the operation was successful. howe ver, a succeeding read will s how that the data is still 0 . only erase operations can convert a 0 to a 1 . 10.6 unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device fast er than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command , 20h. the device then enters the unl ock bypass mode. a two-cycle unlock bypass progr am command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 10.1 on page 32 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contai n the data 90h; the se cond cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 10.1 on page 29 illustrates the algorithm for the program operation. see erase/program operations on page 44 for parameters, and to figure 17.5 on page 44 for timing diagrams.
april 12, 2012 S29AL008J_00_11 S29AL008J 29 data sheet figure 10.1 program operation note see table 10.1 on page 32 for program command sequence. 10.7 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings du ring these operations. table 10.1 on page 32 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the em bedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately te rminates the operation. the chip erase command sequence should be reinitiated once the device has retu rned to reading array data, to ensure data integrity. the system can determine th e status of the erase op eration by using dq7, dq6, dq2, or ry/by#. see write operation status on page 33 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 10.2 on page 31 illustrates the algorithm for the erase operation. see erase/program operations on page 44 for parameters, and figure 17.6 on page 45 for timing diagrams. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
30 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 10.8 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up co mmand. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 10.1 on page 32 shows the address and data requirements for t he sector erase command sequence. the device does not require the system to preprogram the memo ry prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase command s may be written. however, these additional erase commands are only one bus cycle long and should be i dentical to the sixth cycle of the standard erase command explained above. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command migh t not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sect or erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase susp end during the time-out pe riod resets the device to reading array data. the system must rewrite the comm and sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see dq3: sector erase timer on page 37 .) the time-out begins from the rising ed ge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase opera tion immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the st atus of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to write operation status on page 33 for information on these status bits.) figure 10.2 on page 31 illustrates the algorithm for the erase operation. refer to erase/program operations on page 44 for parameters, and to figure 17.6 on page 45 for timing diagrams. 10.9 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for er asure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediatel y terminates the time-out period and suspends the erase operation. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediatel y terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase sus pends? all sectors selected for erasure.) normal read and write timings and command definitions apply. re ading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status on page 33 for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the st atus of the program operation using the dq7 or
april 12, 2012 S29AL008J_00_11 S29AL008J 31 data sheet dq6 status bits, just as in t he standard program operation. see write operation status on page 33 for more information. the system may also write the autoselect comma nd sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence on page 27 for more information. the system must write the erase resume command (address bits are don?t care ) to exit the erase suspend mode and continue the sector erase operation. furthe r writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. figure 10.2 erase operation notes 1. see table 10.1 on page 32 for erase command sequence. 2. see dq3: sector erase timer on page 37 for more information. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
32 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 10.10 command definitions table legend notes table 10.1 S29AL008J command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id, top boot block word 4 555 aa 2aa 55 555 90 x01 22da byte aaa 555 aaa x02 da device id, bottom boot block word 4 555 aa 2aa 55 555 90 x01 225b byte aaa 555 aaa x02 5b sector group protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 byte aaa 555 aaa (sa) x04 00 01 enter secured silicon sector word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon sector word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa cfi query (note 10) word 1 55 98 byte aa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase (note 15) word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 x = don?t care ra = address of the memory location to be read rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18?a12 uni quely select any sector. 1. see table 7.1 on page 13 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a18?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 10. command is valid when device is ready to read array data or when device is in autoselect mode. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. f0 is also acceptable. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid on ly during the erase suspend mode. 15. additional sector erase commands during the time-out period after an initial sector erase are one cycle long and iden tical to the sixth cycle of the sector erase command sequence (sa / 30).
april 12, 2012 S29AL008J_00_11 S29AL008J 33 data sheet 11. write operation status the device provides several bits to determine the stat us of a write operation: dq 2, dq3, dq5, dq6, dq7, and ry/by#. table 11.1 on page 37 and the following subsections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. 11.1 dq7: data# polling the data# polling bit, dq7, indicates to the host sys tem whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for appro ximately 1 s, then the device returns to reading array data. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete , or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum out put described for the embed ded program algorithm: the erase function changes all the bits in a sector to 1 ; prior to this, the device outputs the complement , or 0 . the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the devic e returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. when the system detects dq7 has change d from the complement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 17.8 on page 46 , illustrates this. table 11.1 on page 37 shows the outputs for data# polling on dq7. figure 11.2 on page 36 shows the data# polling algorithm.
34 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet figure 11.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 11.2 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin th at indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 11.1 on page 37 shows the outputs for ry/by#. figures figure 17.1 on page 41 , figure 17.2 on page 42 , figure 17.5 on page 44 and figure 17.6 on page 45 shows ry/by# for read, reset, program, and erase operations, respectively. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
april 12, 2012 S29AL008J_00_11 S29AL008J 35 data sheet 11.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see dq7: data# polling on page 33 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 11.1 on page 37 shows the outputs for toggle bit i on dq6. figure 11.2 on page 36 shows the toggle bit algorithm in flowchart form, and reading toggle bits dq6/dq2 on page 36 explains the algorithm. figure 17.9 on page 46 shows the toggle bit timing diagrams. figure 17.10 on page 46 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii on page 35 . 11.4 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have be en selected for erasure. (the system may use either oe# or ce# to control t he read cycles.) but dq2 cann ot distinguis h whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase su spend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 11.1 on page 37 to compare outputs for dq2 and dq6. figure 11.2 on page 36 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 on page 36 explains the algorithm. see also the dq6: toggle bit i on page 35 subsection. figure 17.9 on page 46 shows the toggle bit timing diagram. figure 17.10 on page 46 shows the differences between dq2 and dq6 in graphical form.
36 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 11.5 reading toggle bits dq6/dq2 refer to figure 11.2 on page 36 for the following discussi on. whenever the system in itially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the t oggle bit is not toggling, the device has completed the program or erase operati on. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device di d not complete the operation successful ly, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 11.2 on page 36 ). figure 11.2 toggle bit algorithm notes 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. start no ye s ye s dq5 = 1? no ye s toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 tw i c e read dq7?dq0 (note 1 ) (notes 1 , 2 )
april 12, 2012 S29AL008J_00_11 S29AL008J 37 data sheet 11.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure conditi on may appear if the syst em tries to program a 1 to a location that is previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and when the operation has exceeded the timing lim its, dq5 produces a 1 . under both these conditions, the system must issue the reset command to re turn the device to reading array data. 11.7 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whet her or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, t he entire time-out also applies after each additional sector erase command. when the time-out is comp lete, dq3 switches from 0 to 1 . the system may ignore dq3 if the system can guarantee that the time between additional sect or erase commands will al ways be less than 50 s. see also sector erase command sequence on page 30 . after the sector erase command sequ ence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the devi ce has accepted the command sequence, and then read dq3. if dq3 is 1 , the internally controlled erase cycle has be gun; all further commands (other than erase suspend) are ignored until the eras e operation is complete. if dq3 is 0 , the device will accept additional sector erase commands. to ensure the command has b een accepted, the system software should check the status of dq3 prior to and following each subsequent se ctor erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 11.1 shows the outputs for dq3. notes 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 37 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. table 11.1 write operation status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
38 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 12. absolute maximum ratings notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 38 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 13.2 on page 38 . 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 38 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the devi ce. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 13. operating ranges note operating ranges define those limits between wh ich the functionality of the device is guaranteed. figure 13.1 maximum negative overshoot waveform figure 13.2 maximum positive overshoot waveform parameter rating storage temperature plastic packages ?65 c to +150 c ambient temperature with power applied ?65 c to +125 c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) ?0.5 v to +12.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma parameter range ambient temperature industrial (i) devices ?40 c to +85 c extended (n) devices ?40c to +125c v cc supply voltages full 2.7 v to 3.6 v regulated 3.0 v to 3.6 v 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
april 12, 2012 S29AL008J_00_11 S29AL008J 39 data sheet 14. dc characteristics 14.1 cmos compatible notes 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. i cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 4. not 100% tested. 5. when device operated in extended temperature range, the currents shall be as follows: i cc3 = 0.2 a (typ), 10 a (max) i cc4 = 0.2 a (typ), 10 a (max) i cc5 = 0.2 a (typ), 10 a (max) parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a wp# input load current v cc = v cc max , wp# = v ss to v cc 25 i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih , v cc = v cc max , byte mode 5 mhz 7 12 ma 1 mhz 2 4 ce# = v il, oe# = v ih, , v cc = v cc max , word mode 5 mhz 7 12 1 mhz 2 4 i cc2 v cc active erase/program current (notes 2 , 3 , 4 ) ce# = v il, oe# = v ih , v cc = v cc max 20 30 ma i cc3 v cc standby current (note 4) oe# = v ih , ce#, reset# = v cc 0.3 v/-0.1v, wp# = v cc or open, v cc = v cc max (note 5) 0.2 5 a i cc4 v cc standby current during reset (note 4) v cc = v cc max ; reset# = v ss 0.3 v/-0.1v wp# = v cc or open, (note 5) 0.2 5 a i cc5 automatic sleep mode (notes 3 , 4 ) v cc = v cc max , v ih = v cc 0.3 v, v il = v ss 0.3 v/-0.1 v, wp# = v cc or open, (note 5) 0.2 5 a v il input low voltage -0.1 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v id voltage for autoselect and temporary sector unprotect v cc = 2.7?3.6 v 8.5 12.5 v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v oh1 output high voltage i oh = -2.0 ma, v cc = v cc min 0.85 x v cc v oh2 i oh = -100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage 2.1 2.5
40 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 15. test conditions figure 15.1 test setup note diodes are in3064 or equivalent. 16. key to switching waveforms figure 16.1 input waveforms and measurement levels table 15.1 test specifications test condition 70 55 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc output timing measurement reference levels 0.5 v cc 2.7 k c l 6.2 k 3.3 v device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v 0.5 v cc output measurement level input 0.5 v cc
april 12, 2012 S29AL008J_00_11 S29AL008J 41 data sheet 17. ac characteristics 17.1 read operations notes 1. not 100% tested. 2. see figure 15.1 on page 40 and table 15.1 on page 40 for test specifications. figure 17.1 read operations timings parameter description speed options jedec std test setup 55 70 unit t avav t rc read cycle time (note 1) min 55 70 ns t avqv t acc address to output delay ce# = v il oe# = v il max 55 70 t elqv t ce chip enable to output delay oe# = v il max 55 70 t glqv t oe output enable to output delay max 30 30 t ehqz t df chip enable to output high z (note 1) max 16 t ghqz t df output enable to output high z (note 1) max 16 t sr/w latency between read and write operations min 20 t oeh output enable hold time (note 1) read min 0 toggle and data# polling min 10 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t sr/w t oh
42 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 17.2 hardware reset (reset#) note not 100% tested. figure 17.2 reset# timings note 1. ce# should only go low after reset# has gone high. keeping ce# low from power up through the first read could cause the first read to retrieve erroneous data. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 t rh reset# high time before read (see note) 50 t rpd reset# low to standby mode 35 s t rb ry/by# recovery time 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms (note 1) t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
april 12, 2012 S29AL008J_00_11 S29AL008J 43 data sheet 17.3 word/byte configuration (byte#) figure 17.3 byte# timings for read operations figure 17.4 byte# timings for write operations note refer to the erase/program operations table for t as and t ah specifications. parameter speed options jedec std description 55 70 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 t fhqv byte# switching high to output active min 55 70 dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
44 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 17.4 erase/program operations notes 1. not 100% tested. 2. see erase and programming performance on page 49 for more information. figure 17.5 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows de vice in word mode. parameter description speed options jedec std 55 70 unit t avav t wc write cycle time (note 1) min 55 70 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 35 35 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 ns t whwl t wph write pulse width high min 25 ns t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
april 12, 2012 S29AL008J_00_11 S29AL008J 45 data sheet figure 17.6 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 33 ). 2. illustration shows de vice in word mode. figure 17.7 back to back read/write cycle timing oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addre ss e s t oh d a t a v a lid in v a lid in v a lid pa v a lid ra t wc t wph t ah t wp t d s t dh t rc t ce v a lid o u t t oe t acc t oeh t ghwl t df v a lid in ce# controlled write cycle s we# controlled write cycle v a lid pa v a lid pa t cp t cph t wc t wc re a d cycle t s r/w
46 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet figure 17.8 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle. figure 17.9 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle. figure 17.10 dq2 vs. dq6 for erase and erase suspend operations note the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
april 12, 2012 S29AL008J_00_11 S29AL008J 47 data sheet 17.5 temporary sector group unprotect note not 100% tested. figure 17.11 temporary sector group unprotect/timing diagram figure 17.12 sector group protect/ unprotect timing diagram note for sector group protect, a6 = 0, a3 = a2 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a3 = a2 = 0, a1 = 1, a0 = 0. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr 12v ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb 0 or 3v sector group p rotect: 150 s sector group unprot ect: 1.5 ms 1 s reset# sa, a6, a3, a2 a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
48 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 17.6 alternate ce# controlle d erase/program operations notes 1. not 100% tested. 2. see erase and programming performance on page 49 for more information. figure 17.13 alternate ce# controlled write operation timings notes 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. parameter speed options jedec std description 55 70 unit t avav t wc write cycle time (note 1) min 55 70 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 35 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 ns t ehel t cph ce# pulse width high min 25 ns t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
april 12, 2012 S29AL008J_00_11 S29AL008J 49 data sheet 18. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0 v, 100,000 cycles, checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10.1 on page 32 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles per sector. 19. tsop and bga pin capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 10 s excludes 00h programming prior to erasure (note 4) chip erase time 10 s byte programming time 6 150 s excludes system level overhead (note 5) word programming time 6 150 s chip programming time byte mode 6.3 80 s word mode 3.2 60 s parameter symbol parameter description test setup package typ max unit c in input capacitance v in = 0 tsop 4 6 pf bga 4 6 c out output capacitance v out = 0 tsop 4.5 5.5 bga 4.5 5.5 c in2 control pin capacitance v in = 0 tsop 5 6.5 bga 5 6.5 c in3 wp# pin capacitance v in = 0 tsop 8.5 10 bga 8.5 10
50 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 20. physical dimensions 20.1 ts 048?48-pin standard tsop note for reference only. bsc is an ansi standard for basic space centering. 3664 \ f16-038.10 \ 11.6.7 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1982) 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. 6. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08mm (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028"). 7. these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. 8. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads.
april 12, 2012 S29AL008J_00_11 S29AL008J 51 data sheet 20.2 vbk048?48-ball fine-pitch ball grid array (bga) 8.15 mm x 6.15 mm 3338 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h b e1 d1 c 0.08 pin a1 corner index mark package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
52 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet 21. revision history section description revision 01 (july 26, 2007) initial release. revision 02 (october 29, 2007) distinctive characteristics corrected number of 64 kbyte / 32 kword sectors global removed 44-pin sop package ordering information removed all leaded package offerings S29AL008J device bus operations table under note 3: removed the line ?if wp# = v hh , all sectors will be unprotected.? cfi query identification string table updated the data for cfi addresses 2c hex & 39 hex S29AL008J command definitions table the 2nd cycle data for the ?unlock bypass rese t? command was updated from 'f0' to '00'. absolute maximum ratings updated v cc absolute maximum rating cmos compatible table updated i cc3 standby current test condition updated maximum value of v ol updated minimum value of v lko figure back to back read/write cycle timing corrected the t sr/w duration revision 03 (march 27, 2008) reset #: hardware reset pin updated current consumption during reset# pulse cmos compatible table updated maximum value of i li updated test condition, typica l and maximum value of icc3 updated test condition, typica l and maximum value of icc4 updated test condition, typica l and maximum value of icc5 updated minimum value of v il added note 5 ordering information updated valid combination ? removed 45 ns, added 70 ns revision 04 (may 23, 2008) global removed fortified bga package option ordering information added the regulated voltage option added the extended temperature range updated the valid combination table pin configuration updated pin configuration table device bus operation updated the S29AL008J device bus operation table and modified note 3 operating ranges added extended temperature range information added regulated voltage revision 05 (august 12, 2008) sector protection/unprotection title changed to sector group protection and unprotection section amended and restated to sector group protection and unprotection temporary sector unprotect title changed to temporary sector group unprotect figure 7.1; title changed to temporar y sector group unprotect operation figure 7.2; title changed to in-system sector protect/unprotect algorithms temporary sector unprotect title changed to temporary sector group unprotect figure 17.11; title changed to temporary sector group unprotect/timing diagram figure 17.12; sector group prot ect/unprotect timing diagram reading toggle bits dq6/dq2 updated figure 11.2 ordering information added ssop56 package option updated the valid combination table connection diagrams added 56-pin shrink small outline package (ssop56)
april 12, 2012 S29AL008J_00_11 S29AL008J 53 data sheet physical dimensions added 56-pin shrink small outline package (ssop56) alternate ce# controlled erase/program operations tds value changed from 45 ns to 35 ns erase/program operation added figure toggle bit ti ming (during embedded algorithm) product selector guide updated table revision 06 (october 29, 2008) customer lockable: secured silicon sector programmed and protected at the factory modified first bullet updated figure secured silicon sector protect verify tsop and pin capacitance updated table revision 07 (february 3, 2009) ordering information updated the valid combination table erase/program operation updated table removed figure toggle bit timing (during embedded algorithm ) erase and programming performance updated table revision 08 (july 9, 2009) general corrected minor typos physical dimensions updated ts048 customer lockable: secured silicon sector not programmed and protected at the factory modified first bullet erase and programming performance updated table revision 09 (february 23, 2010) sector erase command sequence added clar ification regarding additional sector er ase commads during time-out period command definitions table added note 15 to clarify addi tional sector erase commands during time-out period revision 10 (december 9, 2011) ordering information added low-halogen 48-ball bga ordering option reset#: hardware reset pin added sentence regarding use of ce# with reset# reset# timings figure added note revision 11 (april 12, 2012) global removed ssop-56 section description
54 S29AL008J S29AL008J_00_11 april 12, 2012 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2007-2012 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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